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In addition to detailing its roadmap and plans for current leading-edge process technologies, TSMC also shared updates on its N2 node during the Symposiums 2024. This is the company’s first 2nm-class fabrication node, which prominently features gate-all-around transistors. According to TSMC, the N2 node has almost met its target performance and yield goals, setting it on course for high-volume manufacturing in the second half of 2025.
TSMC states that “N2 development is well on track and N2P is next.” Specifically, gate-all-around nanosheet devices are currently achieving over 90% of their expected performance, while the yields of 256 Mb SRAM (32 MB) devices have already exceeded 80%, depending on the batch. All this for a node scheduled to mass-produce in over a year.
By March 2024, the average yield of a 256 Mb SRAM increased to around 70%, up from approximately 35% in April 2023. Device performance has also been on the rise, with higher frequencies being achieved without increasing power consumption.
Interest from chip designers in TSMC’s first 2nm-class gate-all-around nanosheet transistor-based technology is significant as well. The number of new tape-outs (NTOs) in the first year of N2 is more than double that of N5. However, given TSMC’s close collaboration with a few high-volume vendors – notably Apple – NTOs can be misleading since the first year of a new node at TSMC is often capacity constrained, with most of that capacity going to TSMC’s priority partners.
There were significantly more N5 tapeouts in its second year (some of which were N5P), and N2 promises 2.6 times more NTOs in its second year. Thus, the node looks very promising. Indeed, based on TSMC’s slides (which we are unable to republish), N2 is more popular than N3 in terms of NTOs in both the first and the second year of its existence.
Regarding the second year of N2, TSMC plans to introduce its N2P technology in the second half of 2026. N2P promises additional performance and power benefits, including a 15% – 20% improvement in frequency, a 30% – 40% reduction in power consumption, and over 1.15 times the chip density compared to N3E. These are significant benefits provided by the all-new GAA nanosheet transistors.
Finally, for companies seeking the pinnacle of performance, power, and density, TSMC is set to offer their A16 process in 2026. This node will also incorporate backside power delivery, which will increase costs but is expected to substantially enhance performance efficiency and scaling.
