While TSMC wasn’t the pioneer in employing extreme UV (EUV) lithography, with Samsung leading the way, it stands as the largest user of the technology. Through years of operation, TSMC has honed its expertise in EUV, optimizing tool usage to boost efficiency and reduce operational costs. During its European Technology Symposium, the company shared insights into its EUV deployment strategy and its ongoing efforts to integrate EUV more extensively into upcoming process technologies.
Beginning its journey with EUV lithography in 2019 through the N7+ process for Huawei’s HiSilicon, TSMC quickly became a major player. It owned 42% of the global EUV tool base in the early stages, a figure that grew to 50% in 2020, despite increased EUV scanner shipments by ASML. Forecasting into 2024, TSMC’s EUV system count has surged 10 times since 2019, securing 56% of the worldwide EUV market share, outpacing Samsung and Intel despite their expansions in EUV production. This aggressive investment in EUV solidified TSMC’s dominance in the field.
TSMC’s EUV wafer output has seen an astronomical increase, producing 30 times more EUV wafers compared to 2019. This growth far surpasses the tenfold increase in tools, highlighting significant enhancements in EUV productivity, reduced maintenance intervals, and minimal tool downtime, largely thanks to the company’s innovations.
| TSMC’s Leadership in EUV High Volume Manufacturing Data by TSMC (Compiled by AnandTech) |
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| 2019 | 2023 | |||
| Cumulative Tools | 1X | 10X | ||
| Share of Global EUV Installed Base | 42% | 56% | ||
| EUV Wafer Output | 1X | 30X | ||
| Wafer per Day per EUV Tool | 1X | 2X | ||
| Reticle Particle Contamination | 1X | 0.1X | ||
By doubling wafer-per-day-per-tool productivity of its EUV systems since 2019, TSMC optimized EUV exposure dosages and photresist utilization. Additionally, TSMC significantly advanced its pellicle technology for EUV reticles, enhancing their longevity fourfold, increasing output by 4.5 times, and reducing defectivity by a staggering 80 times, thereby boosting productivity and uptime. Details on these advancements remain undisclosed, though they may eventually be shared with the academic community.
| TSMC’s EUV Pellicle Technology vs. Commercial Data by TSMC (Compiled by AnandTech) |
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| Commercial | TSMC (Claimed) | |||
| Output | 1X | 4.5X | ||
| Defectivity | 1X | 0.0125X | ||
| Lifespan | 1X | 4X | ||
Another critical aspect is the high power consumption associated with EUV lithography systems. TSMC has managed to reduce its EUV scanner power usage by 24% using undisclosed energy-saving innovations. They aim to further enhance energy efficiency per wafer per tool by 1.5 times by 2030.
Given the substantial advancements TSMC has achieved in Low-NA EUV lithography, the company is confident about its continuous production of leading-edge chips. While Intel focuses on High-NA EUV for its upcoming sub-18A nodes, TSMC is capitalizing on the mature, optimized Low-NA EUV tools to avoid the challenges of a swift technological transition, further positively impacting cost efficiency.
