Microchip Unveils Flashtec 5016 Controller for Enterprise SSDs

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    <p>Microchip has recently announced the launch of their second PCIe Gen 5 enterprise SSD controller, the Flashtec 5016. Building upon the 4016, this new model is also a 16-channel controller, offering several key enhancements:</p>

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        <li>PCIe 5.0 lane configuration: The 5016 supports operation in x4 or dual independent x2 / x2 mode, compared to the x8, or x4, or dual independent x4 / x2 mode available in the 4016.</li>
        <li>Enhanced DRAM support: The 5016 features four ranks of DDR5-5200, whereas the 4016 is limited to two ranks of DDR4-3200.</li>
        <li>Extended NAND support: While the 4016 supports 2400 MT/s NAND, the 5016 offers support for 3200 MT/s NAND.</li>
        <li>Performance gains: The 5016 is capable of delivering over 3.5M random read IOPS, surpassing the 3M+ IOPS of the 4016.</li>
    </ul>

    <p>Microchip's enterprise SSD controllers offer SSD vendors a high degree of flexibility with significant processing power and accelerators. The 5016 integrates Cortex-A53 cores, allowing SSD vendors to run custom applications pertinent to SSD management. Notably, there are two additional cores in the CPU cluster compared to the Gen 4 controllers. The DRAM subsystem features ECC support, available both out-of-band and in-line, depending on the SSD vendor's preferences.</p>

    <p align="center"><a href="https://images.anandtech.com/doci/21514/flashtec-ml.jpg"><img alt="" src="https://images.anandtech.com/doci/21514/flashtec-ml_575px.jpg"/></a></p>

    <p>At FMS 2024, the company showcased an innovative application of the neural network engines embedded in the Gen5 controllers. Typically, controllers undertake a 'read-retry' operation with changed read-out voltages for flash reads that fail initially. However, Microchip has utilized a machine learning approach to determine the optimal read-out voltage based on the NAND block's health history, leveraging the NN engines in the controller. This method significantly improves read latency and reduces power consumption, thanks to fewer errors occurring on the first read.</p>

    <p>Both the 4016 and 5016 incorporate a single-chip root of trust implementation for ensuring hardware security. A secure boot mechanism with dual-signature authentication protects the controller firmware from unauthorized alterations in the field. The company's controller implementation also boasts benefits in SR-IOV, flexible data placement, and zoned namespaces, along with a 'credit engine' scheme for multi-tenant cloud workloads. These advantages were highlighted in additional demonstrations.</p>

    <p>Microchip's press release featured endorsements from renowned NAND vendors such as Solidigm, Kioxia, and Micron. On the customer side, Longsys has been employing Flashtec controllers in their enterprise solutions alongside YMTC NAND. It is anticipated that this collaboration will continue with the deployment of the new 5016 controller.</p>
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