The rising need for AI and HPC processors is pushing for an increased adoption of sophisticated packaging solutions, especially TSMC’s chip-on-wafer-on-substrate (CoWoS) services. Currently, TSMC is managing to fulfill the demand for this specific packaging technique. Nonetheless, this is a short-term solution as the company revealed its intention last year to substantially boost CoWoS capacity by the close of 2024. However, it has become apparent that a one-time increase in capacity will not suffice, compelling the leading semiconductor manufacturing firm to continually scale up its capabilities.
During its European Technology Symposium held last week, TSMC disclosed its strategy to enhance CoWoS capacity at an annual growth rate exceeding 60% until at least 2026. Consequently, TSMC’s CoWoS capacity is set to exceed four times the levels of 2023 by the termination of this timeframe. Moreover, TSMC is developing new CoWoS variants (specifically CoWoS-L), aimed at facilitating the creation of system-in-packages (SiPs) as large as eight reticle sizes. Even with a four-fold increase in CoWoS capacity over three years, meeting the escalating demand might still pose a challenge. Fortunately, the expansion in CoWoS-like capabilities is not solely TSMC’s burden to bear, as various third-party assembly and testing (OSAT) firms are also augmenting their capacities to meet the advanced packaging demands.
Beyond CoWoS, TSMC is actively working to extend the capacity of another advanced packaging technology – the system-on-integrated chips (SoIC) 3D stacking technique. With the anticipated rise in adoption rates for SoIC packaging methods in the near future, TSMC plans to double SoIC capacity annually, aiming for an eight-fold increase from 2023 figures by the end of 2026.
In summary, TSMC anticipates a significant uptake in sophisticated SiPs for critical applications such as AI and HPC, necessitating an expansion in both CoWoS and SoIC 3D stacking technologies to meet the production needs of these advanced processors.
